1. Field of the Invention
The present invention relates generally to techniques to improve efficiency in a processor which processes instructions having a variety of lengths, and, more particularly, to advantageous techniques for storing predecode information in a predecode repair cache for instructions that span across two or more cache lines.
2. Relevant Background
Many processors support instruction sets having variable length instructions. For example, a processor's instruction set may consist of 32-bit instructions and 16-bit instructions. A processor may also have a hierarchical memory configuration with multi-levels of caches including an instruction cache, a data cache, and system memory, for example. If the processor also has a deep execution pipeline that operates at a high clock rate with short duration pipeline stages, it is also likely that the processor has a predecode stage to preprocess the instructions in order to simplify a subsequent decode stage and, thus, streamline the pipeline. The predecode pipeline stage is commonly operative during an instruction cache miss to partially decode instructions that are fetched due to the instruction miss. The predecode information is written into the instruction cache along with the fetched instructions.
In a variable length instruction processor, the instructions fetched due to a miss may be of varying length and the longer instructions may span across two cache lines. For instructions that span across two cache lines, both portions of the instruction must be fetched in order to properly predecode the instruction which increases the complexity of the predecode function and may impact performance and power utilization.